`include "defines.v"

module pc_reg(
input  wire             		clock,
	input  wire            		reset,
	input wire[`STALL_BUS]		stall,
	input wire[`RegisterBus]	branch_address,
	input wire					branch_sig,
	output reg[`DataBus]   		pc,
	output reg             		ce
);

always @ (posedge clock) begin
		if (reset == `ResetEnable) begin
			ce <= `ChipDisable;
		end else begin
			ce <= `ChipEnable;
		end
	end
	
	always @ (posedge clock) begin
		if (ce == `ChipDisable) begin
			pc <= 32'h00000000;
		end else if(stall[0] == 1'b0) begin//stall无效时PC自加
			if(branch_sig == 1'b1) begin
				pc <= branch_address;
			end else begin
				pc <= pc + 4;
			end
		end
	end
endmodule